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coredds handbook
actel corporation, mountain view, ca 94043 ? 2006 actel corporation. all rights reserved. printed in the united states of america part number: 50200078-0 release: september 2006 no part of this document may be copied or reproduced in any form or by any means without prior written consent of actel. actel makes no warranties with respect to this documentation and disclaims any implied warranties of merchantability or fitn ess for a particular purpose. information in this document is subject to change without notice. actel assumes no responsibility for any errors that may appear in this document. this document contains confidential proprietary information that is not to be disclosed to any unauthorized person without prior written consent of actel corporation. trademarks actel and the actel logo are registered trademarks of actel corporation. adobe and acrobat reader are registered trademarks of adobe systems, inc. all other products or brand names mentioned are trademarks or registered trademarks of their respective holders.
coredds handbook 3 table of contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 core overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 functional descripti on . . . . . . . . . . . . . . . . . . . . . . . 9 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 lut initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 phase dithering and phase quantizer . . . . . . . . . . . . . . . . . . . . . . . 15 2 tool flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 installation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 pre-synthesis simulation flow . . . . . . . . . . . . . . . . . . . . . . . . . . 22 synthesis in the libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 place-and-route in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 interface descriptions . . . . . . . . . . . . . . . . . . . . . . . . 25 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 configuration parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 testbench operation and modifica tion . . . . . . . . . . . . . . . 29 verification testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 a coredds configurations . . . . . . . . . . . . . . . . . . . . . . 31 sample configuration file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 evaluation version configuration of coredds . . . . . . . . . . . . . . . . . 32 b product support . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 customer service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 actel customer technical support center . . . . . . . . . . . . . . . . . . . . 35 actel technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 contacting the customer technical support center . . . . . . . . . . . . . . . 36 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

coredds handbook 5 introduction core overview coredds is an rtl generator that produces an actel fpga-optimized direct digital synthesizer (dds) core. dds digitally generates a complex or re al-valued sine wave. due to the digital nature of the dds functionality, it offers fast switching between output sine wave frequencies, fine frequency resolution, and operations over broad frequency range. 1 a dds or a numerically controlled oscillator (nco) is an important component in many digital communication systems. quadrature synthesizers are used for constructing digital down and up converters, constructing demodulators, and implementing va rious types of modulation schemes, including phase shift keying (psk), frequency shift keying (fsk), and minimum shift keying (msk). a common method for digitally generating a complex or real valued sinusoid employs a lookup table (lut) scheme. the lookup table stores samples of a sinusoid. a digital integrator is used to generate a suitable phase argument that is mapped by the lookup table to the desired output waveform. figure 1 depicts a simplified view of the coredds inputs and outputs. figure 1. coredds simplified view depending on the core configuration, coredds can generate a sine or cosine waveform, as well as the complex sinusoid. in the latter case, the core generator creates two data outputs with a sine wave (imaginary part of the complex sinusoid) present on the first output, and the cosine wave (real part of the complex sinusoid) present on the second output. output valid goes active when the dds generates its first valid output sample. the dds can be set to generate a waveform of a constant frequency and ph ase shift. particular values of these parameters and the waveform bit resolution are set at configuration time. one can also configure the core to have optional phase and/or frequency modulation ports so that the output frequency and phase can be modulated at run time. 1. goldberg, bar-giora, 1999, digital frequency synthesis demystified , llh technology publishing. dd s optional phase mo d ulation optional frequency mo d ulation sin or cos optional cos vali d
introduction 6 coredds handbook a user configures the dds via a configuration text file by setting desired parameter values. for a detailed description of the configuration parameters, refer to configuration parameters on page 26 . a typical application using the dds is shown in figure 2 on page 6 . the dds is used in a communication system as a quadrature intermediate frequency (if) carrier oscillator to implement a simple if modulator. two mixers modulate baseba nd quadrature data, i(t) C q(t), to create a composite output if signal. similarly, the dds can be used to demodulate an i-q composite signal. figure 2. dds typi c al appli c ation hardware implementation the dds engine implements three different hardware architectures: ?small lut ?big lut ? parallel cordic a user specifies a desired architecture at configuration time. architectures on page 12 provides a detailed explanation of the dds architectures. dd s cos( t) sin( t) i(t) q(t) if s i g nal qua d rature oscillator
core overview coredds handbook 7 utilization and performance the coredds engine has been implemented in several actel fpga families. a summary of the data for coredds is listed in table 1 . table 1. coredds devi c e utilization and performan c e device engine architect cells or tiles utilization % ram blocks clock rate (mhz) comb seq total utilized available on chip fusion speed grade C2 afs600 small lut 1,185 506 1,691 12% 4 24 104 afs600 big lut 548 214 762 6% 1 24 109 afs600 cordic 7,500 1,654 9,154 66% 0 24 82 proasic?3/e speed grade C2 a3p600 small lut 1,194 508 1,702 12% 4 24 112 a3p600 big lut 556 217 773 6% 1 24 101 a3p600 cordic 7,433 1,643 9,076 66% 0 24 85 proasic plus ? speed grade std apa600 small lut 1,726 447 2,173 11% 8 56 68 apa600 big lut 852 213 1065 5% 2 56 64 apa600 cordic 10,342 1,623 11,965 56% 0 56 45 axcelerator? speed grade C2 ax500 small lut 858 417 1,275 16% 4 16 141 ax500 big lut 399 226 625 8% 1 16 191 ax500 cordic 3,751 1,603 5,354 66% 0 16 138 rtax speed grade C1 rtax250s small lut 858 417 1,275 32% 4 16 100 rtax250s big lut 399 226 625 16% 1 16 127 rtax1000s cordic 3,751 1,603 5,354 33% 0 16 102 note: data in this table were achieved using typical synthesis an d layout settings. coredds configuration parameters were set as shown in table 2 on page 8 .
introduction 8 coredds handbook table 2. dds test configurations parameter small lut big lut cordic name comment module_name testdds testdds testdds function output waveform: ain(0), xos(1), quad(2) 0 1 2 architecture small lut(0), big lut(1), cordic(2) 0 1 2 phacc_mode phase increment: constant(0), port (1) 0 0 0 phase_const phase increment constant value 977 317 977 phase_modulation none(0), constant(1), port(2) 1 1 1 phase_mod_const phase modulation constant value 12 12 12 dithering off(0), on(1) 1 1 0 dith_attenuation dithering attenuation value 1 1 x phacc_bitsize bit width of the phase accumulator 24 15 24 slicer_bitsize bit width of a slicer 12 7 12 wave_bitsize waveform bit resolution 14 12 14 fpga_family lang verilog verilog verilog
coredds handbook 9 1 functional description theory of operation a high-level view of the dds core is presented in figure 1-3 . the phase accumulator computes a phase slope with high bit resolution that is mapped to a sinusoid (possibly complex) by the lookup table (lut). the phase quantizer (slicer) accept s the high-precision phase angle and generates a lower precision representation of the angle denoted as (n) in figure 1-3 . the slicer output bit resolution is denoted as b_ (n) bits. this value is presented to the address port of a lookup table that contains the pre-computed value of sin( (n)) and/or cos( (n)) in a proper memory cell. figure 1-1. lut-base d dds simplified blo c k diagram the fidelity of a signal formed by recalling samples of a sinusoid from a lookup table is affected by both the phase and amplitude quantization of the process. the length and width of the lookup table affect the signal's phase angle re solution and the signal's amplitude resolution respectively. these resolution limits are equivalent to time base jitter and to amplitude quantization of the signal, and add spectral modulation lines and a white broa d-band noise floor to the signal's spectrum. direct digital synthesizers use an addressing scheme with an appropriate lookup table to form samples of an arbitrary frequency sinusoid. if an analog output is required, the dds presents these samples to a digital to analog co nverter (dac) and a low-pass filter to obtain an analog waveform with the specific frequency structure. of course, the samples are also commonly used directly in the digital domain. the lookup table traditionally stores uniformly spaced samples of a cosine and a sine wave. these samples represent a single cycle of a complex sinusoid. the cycle contains n = 2 b_ (n) complex samples and corresponds to specific values of the sinusoid's argument, (n), as shown in eq 1 . eq 1 where n is the time series sample index. quarter period wave symmetry in the basis waveform can be exploited to construct a dds that uses shortened tables. in this case, the two most significant bits of the quantized phase angle are used to ? + ? (n) phase quantizer s in c os lut ta b le depth = sin( (n)) cos( (n)) phase accumulator phase increment re g ister ? b _ (n) b its (n) 2 b _ (n) n () n 2 n ------ =
functional description 10 coredds handbook perform quadrant mapping. this implementation resu lts in a more area-efficient implementation because the memory requirements are minimized; the required lut can be implemented using one quarter of the necessary ram capacity. since thi s memory-saving technique may slightly slow down the dds implementation, it is left up to the user to decide which implementation better matches design needs 2 . output frequency the output frequency, ? out , of the dds waveform is a function of the system clock frequency, ? clk , the number of bits in the phase accumulator, b_ ? (n), and the phase increment value, ? . output frequency in hertz is defined as shown in eq 2 . eq 2 for example, if the dds parameters are ? clk = 96 mhz b_ ? ( n ) = 12 ? = 62 the output frequency will be . the phase increment value, ?, required to generate an output frequency, ? out hz, is shown in eq 3 . eq 3 2. also for short tables, fpga logic resources ar e actually minimized by storing a complete cycle. f out f clk ? 2 b_ ? n () ----------------- hz = f out 96 10 6 62 ?? 2 12 ----------------------------- 1 453 125 mhz ,, == ? f out 2 b_ ? n () f clk ------------------------- - =
theory of operation coredds handbook 11 frequency resolution the frequency resolution of the synthesizer is a function of the clock frequency and the number of bits employed in the phase accumulator. the frequency resolution can be determined using eq 4 . eq 4 for example, for the dds parameters ? clk = 96 mhz b_ ? ( n ) = 32 the frequency resolution is . spectral purity typically, the spectral purity of an oscillator is measured by its signal-to-noise ratio (snr) and its spurious free dynamic range (sfdr). the snr of a digitally synthesized sinusoid is a ratio of the signal power relative to the unavoidable quanti zation noise inherent in its discrete-valued representation. snr is a direct result of the finite precision with which the dds represents the output sine and cosine waveforms. increasing the output precision results in an increased snr. eq 5 estimates the snr of a given sinusoid with output precision b_s bits: snr = 6 b_s C 1.8 (db) eq 5 each additional bit of output precision leads to an additional 6 db in snr. the sfdr of a digital sinusoid is the power of the primary or desired spectral component relative to the power of its highest-level harmonic component in the spectrum. harmonic components manifest themselves as spikes or spurs in the spectral representation of a digital sinusoid and occur at regular intervals and are also a direct consequence of finite precision. however, the effect of the spurs is often severe because they can cause substantial inter-modulation products and undesirable replicas of the mixed signal in the spectrum, leading to poor reco nstruction of the signal at the receiver. the direct effect of finite precision varies between architectures, but the effect is augmented because, due to resource usage constraints, the dds does not usually use the full accumulator precision in the polar-to-cartesian transformation. one can mitigate the quantization effects with phase dithering, which attempts to convert the spurious signal energy to evenly distributed noise. dithering randomizes the truncated phase value by adding a small amount of noise prior to phase truncation. this process removes some of the periodicity in the phase, reducing the spur magnitude in the sinusoidal spectrum. f f clk 2 b_ ? n () ----------------- = f f clk 2 b_ ? n () ----------------- 96 10 6 ? 2 32 ------------------ - 0.0223517 hz == =
functional description 12 coredds handbook ar c hite c tures coredds supports big lut, small lut, and cordic architectures. big lut architecture the big lut architecture, shown in figure 1-2 , stores a complete cycle (360 degrees) of the sine/cosine waveforms in the lut. use the big lut architecture if the design requires very high speed sinusoidal waveforms, and the design can use large quantities of internal memory. the phase accumulator uses either constant phase increment, ?, stored in a phase increment register, or an input signal, ?, coming from an optional frequency modulation port. a phase offset can be added to a phase signal at a phase accumulator output. depending on user configuration, the phase offset is a constant user-defined value of ? 0 , or a variable signal, ? 0 , coming from an optional phase modulation port. it is also possible to add a dithering signal to the phase prior to truncating extra phase bits. output of the phase quantizer directly addresses the lut. because the internal memory holds all possible output values for a given angular and magnitude precision, the generated waveform has the highest spectral purity for that parameter set (assuming no dithering). the big lut architecture also uses the fewest fabric tiles for a given set of precision parameters. figure 1-2. big lut ar c hite c ture phase a cc umulator phase in c rement register phase offset register dither phase quantizer sincos lut (n) b_ (n) bits b_s bits b_s bits sin( (n)) c os( (n) ) table depth = ? ? 0 ? ? 0 ? (n) + + + 2 b_ (n)
architectures coredds handbook 13 small lut architecture in a small lut architecture, depicted in figure 1-3 , the lut only stores 90 degrees of the sine or cosine waveform (or 45 degrees of the sine and cosine waveforms). all other output values are derived from these values based on the angle value (n). use the small lut architecture to reduce on-chip memory usage. the phase generation part of the small lut architecture is identical to that of the big lut architecture described in big lut architecture on page 12 . the quantized phase, (n), is mapped to the first quadrant (0C90 degrees) of a pola r angle. the sine/cosine samples obtained from the lut are then processed to restore proper polar quadrant mapping. because a small rom implementation is more likely to have periodic value repetition, the resulting waveforms sfdr is generally lower than that of the large rom architecture. however, it is often possible to mitigate this reduction in sfdr with phase dithering. figure 1-3. small lut ar c hite c ture cordic architecture the cordic algorithm, which can calculate trig onometric functions such as sine and cosine, provides a high-performance solution for very high precision oscillators in systems where internal memory is at a premium. the cordic algorithm is based on the concept of complex phasor rotation by multiplication of the phase angle by successively smaller constants. in digital hardware, the multiplication is by powers of two only. therefore, the algorithm can be implemented efficiently by a series of simple binary sh ifts and additions/subtractions. in a dds, the cordic algorithm must compute the sine and cosine of an input phase value by iteratively shifting the phase angle to approximate the cartesian coordinate values for the input phase quantizer sincos lut (n) b_ (n) bits b_s bits b_s bits sin( (n)) cos( (n)) table depth = ? ? 0 phase a cc umulator phase in c rement register phase offset register dither ? ? 0 ? (n) + + + restore proper quadrant mapping map phase on quadrant 1 2 b_ (n)-3
functional description 14 coredds handbook angle. at the end of the cordic iteration, the x and y coordinates for a given angle represent the cosine and sine of that angle, respectively. see the corecordic cordic rtl generator datasheet for more information. figure 1-4 shows the cordic-based dds architecture. since the cordic architecture eliminates the sine/cosine lut by real-time wave form computation, it can provide higher phase resolution, thus reducing spurious signals caused by phase quantization. while in the lut-based architectures the feasible lut size limits bit resolution at the phase quantizer output, the cordic dds architecture is virtually free of this limitation. in many cases, the cordic-based architecture does not utilize the phase quantizer, since the cordic can accept all bits of the phase generator. coredds still enables a user to infer the phase quantizer as well as dither the phase signal if there is a desire to do so. figure 1-4. cordic-based dds ar c hite c ture lut initialization to support the actel one-chip solution, coredd s implements an intern al sine/cosine table generator to initialize the sincos lut ( figure 1-5 on page 15 ). the generator is based on a small bit-serial cordic engine that calculates the ne cessary sin/cos table entries. cordic-generated sine wave samples are approximations of a precise sine wave. in order to store the lut precise sine wave values, the approximations sin' and cos' need to be truncated to discard bits that are not accurate. the bit-serial cordic engine is relatively slow, but since the initialization takes place only on power-on, this does not impact the dds performance. a power-on signal (asynchronous re set) kicks off an initialization state machine. it generates the necessary signals to control the cordic engine as well as the ram block, and provides a write ? + ? 0 + ? phase a cc umulator phase in c rement register phase offset register ? ? 0 fast cordic map phase on quadrants 1, 4 restore proper quadrant mapping sin( ? ) c os( ? ) ? (n)
phase dithering and phase quantizer coredds handbook 15 address for the ram block. once the initializatio n is done, the ram block switches to read-only mode. figure 1-5. sine/cos ine lut initialization phase dithering and phase quantizer a source of dithering noise generates a uniforml y distributed zero-mean pseudorandom signal in a range from Cb/2 to b/2, where b is the most sign ificant bit to be discarded as a result of phase quantization. from the spur level standpoint, it is often beneficial to use a dithering signal with a smaller variance. coredds supports configurable atte nuation of the dithering signal by a factor of 1/2 dith_attenuation . the phase quantizer implements the round-to-nearest-even algorithm, which is commonly recognized as a standard way of rounding numbers. round-to-nearest-even is the default rounding scheme of the ieee floatingCpoint standard. 3 small bit-serial cordic initialization state ma c hine power-on ? angle argument control sin? c os? round and extra c t a cc urate bits ram blo c k sin c os write address and control initialization done 3. parhami, behrooz, 2000, computer arithmetic, algorithms and hardware designs , oxford university press, pp 287-291.

coredds handbook 17 2 tool flows coredds is licensed in two ways. depending on your license, tool flow functionality may be limited. evaluation: rtl source code with limited parameters and corresponding testbench are provided. evaluation version is fully supported in the actel libero? integrated design environment (ide) full version: complete fully user configurable rtl source code is provided along with behavioral testbenches. coredds is a combination of verilog or vhdl source files, microsoft windows? command line programs that generate other source files, and auxiliary files necessary to integrate the core into libero ide design flow. the rtl sources are optimized for actel fpga devices. the majority of tool flows are common to both the full and evaluation versions of the core. any differences are outlined below. installation flow this section describes coredds installation flow and provides implementation hints. check the coredds web page for updates to the installation instructions. in order to install coredds you must create a libero ide project first. installing coredds evaluation version to install the coredds evaluation version: 1. start libero ide and create a new project. ? choose a project name (testdds, for example), a location (f:\actelprj, for example), and an hdl type (verilog or vhdl). ? select the targeted fpga family, device, and package (fusion family, afs600 device, and 256 fbga package, for example). click next . ? select integrated tools synplify ? and model sim ?. click next . ?click finish . 2. using windows explorer, create the subfolders \source and \package in the project folder \testdds.
tool flows 18 coredds handbook 3. unzip evaldds.zip to extract files in the newly created subfolder \testdds\source . the subfolder now contains the following files: ? coredds_eval.exe ? corecordic.exe ? dds_config.txt ?dds_top.sdc ?subfolder coredds_verilog , which contains the following files: dds.v kit.v dds_tb.v ?subfolder coredds_vhdl , which contains the following files: dds.vhd kit.vhd rtl_pack.vhd bhv_pack.vhd bhv.vhd dds_tb.vhd 4. modify the lang parameter of the dds_config.txt file as desired, using a text editor. note: the evaluation version can only accept the user-defined parameters outlined in table a-1 on page 32 . 5. run coredds_eval by typing the following co mmand at the command prompt: f:\actelprj\testdds\source > coredds_eval dds_config.txt this creates a few more files in the \source subfolder, dds_batch.bat among them. 6. run dds_batch.bat by double-clicking its icon in wind ows explorer. this creates three new folders within the \source subfolder: \hdl , \package , and \stimulus, filled with necessary source files. all source files stored in these folders are imported into the libero ide project. 7. go back to the libero ide and import the source files from the folders \testdds\source\hdl and \testdds\source\stimulus . if the language selected is vhdl, import the source files from the folder \ testdds\source\package as well. note: normally you need to import files from the \testdds\source\hdl subfolder to the hdl source files folder of the libero ide project; import files from the \testdds\source\stimulus subfolder to the stimulus files folder of the libero ide project; and import files from the \testdds\source\package subfolder to the package folder of the libero ide project. refer to libero ide documentation for specific instructions.
installation flow coredds handbook 19 8. import the constraint file \testdds\source\dds_top.sdc to the constraint files folder of the libero ide project. 9. in the libero ide, set dds_top as a root. 10. successful installation of coredds source files results in a libero ide sc reen similar to the one shown in figure 2-1 (verilog project) or figure 2-2 on page 20 (vhdl project). figure 2-1. libero ide dds verilog proje c t settings
tool flows 20 coredds handbook figure 2-2. libero ide dds vhdl proje c t settings installing coredds full version to install the coredds full version: 1. start libero ide and create a new project. ? choose a project name (testdds, for example), a location (f:\actelprj, for example), and an hdl type (verilog or vhdl). ? select the targeted fpga family, device, and package (fusion family, afs600 device, and 256 fbga package, for example). click next . ? select integrated tools synplify and model sim . click next .
installation flow coredds handbook 21 ?click finish . 2. using windows explorer, create the subfolders \source and \package in the project folder \testdds. 3. unzip coreldds.zip to extract files in the newly created subfolder \testdds\source . the subfolder now contains the following files: ? coredds.exe ? corecordic.exe ? dds_config.txt ?dds_top.sdc ?subfolder coredds_verilog , which contains the following files: dds.v kit.v dds_tb.v ?subfolder coredds_vhdl , which contains the following files: dds.vhd kit.vhd rtl_pack.vhd bhv_pack.vhd bhv.vhd dds_tb.vhd 4. modify the configuration parameter of the dds_config.txt file as desired, using a text editor. valid values of the core parameters are shown in table 3-2 on page 26 . note: keep the original format of the configurat ion file. modify only the parameter values. 5. run coredds by typing the following command at the command prompt: f:\actelprj\testdds\source > coredds dds_config.txt this creates a few more files in the \source subfolder, dds_batch.bat among them. 6. run dds_batch.bat by double-clicking its icon in wind ows explorer. this creates three new folders within the \source subfolder: \hdl , \package , and \stimulus filled with necessary source files. all source files stored in these folders are to be imported into the libero ide project. 7. go back to the libero ide and import the source files from the folders \testdds\source\hdl and \testdds\source\stimulus. if the language selected is vhdl, import the source files from the folder \testdds\source\package as well. note: normally you need to import files from the \testdds\source\hdl subfolder to the hdl source files folder of the libero ide project; import files from the \testdds\source\stimulus subfolder to the stimulus files folder of the libero ide project;
tool flows 22 coredds handbook and import files from the \testdds\source\package subfolder to the package folder of the libero ide project. refer to libero ide documentation for specific instructions. 8. import the constraint file \testdds\source\dds_top.sdc to the constraint files folder of the libero ide project. 9. in the libero ide, set dds_top as a root. 10. successful installation of coredds source files results in a libero ide sc reen similar to the one shown in figure 2-1 on page 19 (verilog project) or figure 2-2 on page 20 (vhdl project). pre-synthesis simulation flow pre-synthesis simulation verifies the correctness of the code generated. use the following procedure to run pre-synthesis simulation in libero ide. the same procedure applies to both evaluation and full versions. to run pre-synthesis simulation: 1. in the libero ide gui, select options > project settings . in the project settings window, choose the simulation tab. specify the simulation run time Call . click ok . 2. run simulation. ? click the simulation C model sim button in the libero ide gui design flow window to start pre-synthesis simulation. ? when prompted, set up stimulus: select associate with stimulus . click ok. if in a verilog project, select the following stimulus files: dds_tb.v goldsin.v goldphase.v if in a vhdl project, select the following stimulus files: dds_tb.vhd goldsin.vhd goldphase.vhd bhv_pack.vhd bhv.vhd click ok. model sim starts automatically.
synthesis in the libero ide coredds handbook 23 3. since lut-based architectures may take significant time, depending on the actual core configuration parameters, the model sim screen notifies you of the estimated simulation length, as follows: # ---------------------------------------------------------------- # initializing a lut... it takes simulation time of about 216 us # ---------------------------------------------------------------- 4. successful simulation results in the following message on the model sim screen: ############################## # dds test passed ############################## synthesis in the libero ide click the synthesis button in the libero ide gui. the synthesis window appears, displaying the synplicity project. set synplicity to use the verilog 2001 standard if verilog is being used. to start synthesis, click the run button. pla c e-and-route in libero ide once the synthesis has successfully completed, click the place&route button in the libero ide gui to invoke designer. make sure de signer imports the constraints file dds_top.sdc .

coredds handbook 25 3 interface descriptions ports the port signals for coredds are defined in table 3-1 and illustrated in figure 3-1 on page 26 . table 3-1. i/o signal des c riptions name type description ngrst input global asynchronous reset. active low. rstinit input synchronous reset for the lut initialization circuitry. active high. rstph input synchronous reset for the phase generation module. active high. can be used to reset phase generation circuitry without disturbing the initialized lut. clk input system clock. active rising edge. clkeninit input clock enable signal for the lut initialization circuitry. active high. clkenph input clock enable signal for the phase generation circuitry. active high. portphmod [phacc_width-1:0] input phase modulation port. unsigned data present at the port add up to phase accumulator output. the port bit width equals the configurable phase accumulator bit width of phacc_width. portfreqmod [phacc_width-1:0] input frequency modulation port. unsigned data present at the port are used to increment phase accumulator. the port bit width equals the configurable phase accumulator bit width of phacc_width. outsin [wordsize-1:0] output output data bus carrying digitized waveform. user defined bus width = wordsize. the bus carries a digitized sine wave if the core is configured to generate a real or complex sinusoid. it carries a cosine waveform if the core is configured to genera te a real cosine function. outcos [wordsize-1:0] output output data bus carrying digitized cosine waveform. user defined bus width = wordsize. the bus carries a digitized cosine wave if the core is configured to generate a complex sinusoid. if configured differently, the signal of the bus is undefined. initdone output goes active (high) upon completion of the lut initialization. validout output goes active (high) when the core starts generating valid output waveform samples.
interface descriptions 26 coredds handbook figure 3-1. coredds i/o signals configuration parameters coredds generates the dds engine rtl code based on parameters set by the user. coredds supports the variations specified in table 3-2 . dds ngrst rstinit rstph c lk c lkeninit c lkenph portphmod portfre q mod outsin outcos initdone validout table 3-2. coredds configuration parameters name valid value description module_name string of 50 characters name of the gene rated rtl code module or entity function 0, 1, or 2 output waveform type: sine (0), cosine (1), or quadrature (2) architecture 0, 1, or 2 defines dds engine architecture: small lut (0), big lut (1), or cordic(2) phacc_mode 0 or 1 sets a source of the phase increment value for the phase accumulator: constant (0), or the frequency modulation port portfreqmod (1). phase_const unsigned phacc_width- bit number value of the constant phase increment for the phase accumulator. it is used if phacc_mode is set to 0.
configuration parameters coredds handbook 27 phase_modulation 0, 1, or 2 sets a phase modulation mode: no phase modulation (0), constant phase shift (1), phase shift is obtained from the phase modulation port, portphmod (2). phase_mod_const unsigned phacc_width- bit number value of the constant phase shift. it is used if phase_modulation is set to 1. dithering 0 or 1 enables dither mode. phase gets dithered if this parameter is set to 1. dithering takes effect only if the phase accumulator bit width phacc_width is larger than bit width slice_width at the output of the phase quantizer. dith_attenuation 0 to 7 pseudorandom dithering signal attenuation factor. dithering takes effect if the phase accumulator bit width, phacc_width, is not less than the sum of the phase quantizer output bit width, slice_width, and the attenuation factor. dith_attenuation = 0 means there is no attenuation; dith_attenuation = 7 means the max attenuation applies. phaseacc_bitsize 4 to 32 sets the bit width, phacc_width, of the phase accumulator. slicer_bitsize 4 to 32 sets the bit width, slice_width, of the phase quantizer output. with lut-based dds architectures, the quantizer bit width is limited by the on-chip ram capacity available on a selected part. wave_bitsize 4 to 32 sets the generated waveform bit resolution. fpga_family af, pa3, apa, or ax identifies actel family of fpga devices: fusion (af ), proasic3/e (pa3), proasic plus (apa), or axcelerator/ rtax (ax). lang verilog or vhdl identifies hardware description language for the rtl code and testbench to be generated. table 3-2. coredds configurat ion parameters (continued) name valid value description

coredds handbook 29 4 testbench operation and modification verifi c ation testben c h included with the releases of coredds is a verification testbench that verifies operation of the coredds engine. a simplified block diagram of the verification testbench is shown in figure 4-1 . the verification testbench instantiates the dds engine configured by the user, as well as a signal generator that provides necessary clock, reset, and other signals. the testbench compares the actual dds output(s) and golden test vectors, golden sine and/or golden cosine, automatically generated by coredds. coredds generates verilog or vhdl testbench behavioral code based on the user selection of the core language. figure 4-1. coredds verifi c ation testben c h the testbench instantiates the dds engine and veri fies it is configured according to the user- defined parameters 4 . the same testbench can be used for pre-synthesis and post-synthesis simulation. a simulation tool displays the verification result. 4. the verification testbench assu mes no modulation ports are present. dds engine ngrst rstinit rstph c lk c lkeninit c lkenph outsin outcos validout signal generator compare golden ve c tor generator golden sine golden cosine

coredds handbook 31 a coredds configurations the user defines the dds engine conf iguration via a configuration file. sample configuration file module_name testdds function 0 architecture 0 phacc_mode 0 phase_const 977 phase_modulation 1 phase_mod_const 12 dithering 1 dith_attenuation 1 phaseacc_bitsize
coredds configurations 32 coredds handbook 24 slicer_bitsize 12 wave_bitsize 14 fpga_family ax lang verilog evaluation version configuration of coredds the evaluation version implements the dds engine configuration shown in table a-1 . table a-1. coredds evaluation version configuration name value module_name testdds function 0 architecture 0 phacc_mode 0 phase_const 569 phase_modulation 1 phase_mod_const 20 dithering 1 dith_attenuation 1 phaseacc_bitsize 20 slicer_bitsize 8 wave_bitsize 8 fpga_family af lang verilog or vhdl
evaluation version configuration of coredds coredds handbook 33 the user can only select the hdl type by changing the lang parameter value. any other modifications of the evaluation configuration file are ignored. the evaluation configuration file is shown below: module_name testdds function 0 architecture 0 phacc_mode 0 phase_const 569 phase_modulation 1 phase_mod_const 20 dithering 1 dith_attenuation 1 phaseacc_bitsize 20
coredds configurations 34 coredds handbook slicer_bitsize 8 wave_bitsize 8 fpga_family af lang verilog
coredds handbook 35 b product support actel backs its products with various support se rvices including customer service, a customer technical support center, a web site, an ftp site, el ectronic mail, and worldw ide sales offices. this appendix contains information about contacti ng actel and using these support services. customer servi c e contact customer service for non-technical prod uct support, such as product pricing, product upgrades, update information, order status, and authorization. from northeast and north central u.s.a., call 650.318.4480 from southeast and southwest u.s.a., call 650. 318.4480 from south central u.s.a., call 650.318.4434 from northwest u.s.a., call 650.318.4434 from canada, call 650.318.4480 from europe, call 650.318.4252 or +44 (0) 1276 401 500 from japan, call 650.318.4743 from the rest of the world, call 650.318.4743 fax, from anywhere in the world 650.318.8044 a c tel customer te c hni c al support center actel staffs its customer technical support center with highly skilled engineers who can help answer your hardware, software, and design questions. the customer technical support center spends a great deal of time creating application notes and answers to faqs. so, before you contact us, please visit our online resources. it is very likely we have already answered your questions. a c tel te c hni c al support visit the actel customer support website ( www.actel.com/custsup/search.html ) for more information and support. many ans wers available on the searchable web resource include diagrams, illustrations, and links to other resources on the actel web site. website you can browse a variety of technical and non-technical information on actels home page , at www.actel.com .
product support 36 coredds handbook conta c ting the customer te c hni c al support center highly skilled engineers staff the technical support center from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. several ways of contacting the center follow: email you can communicate your technical questions to our email address and receive answers back by email, fax, or phone. also, if you have design problems, you can email your design files to receive assistance. we constantly monitor the email account throughout the day. when sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request. the technical support email address is tech@actel.com . phone our technical support center answers all calls. the center retrieves information, such as your name, company name, phone number and your question, and then issues a case number. the center then forwards the information to a queue where the first available application engineer receives the data and returns your call. the phone hours are from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. the technical support numbers are: 650.318.4460 800.262.1060 customers needing assistance outside the us time zones can either contact technical support via email ( tech@actel.com ) or contact a local sales office. sales office listings can be found at www.actel.com/contact/offices/index.html .
coredds handbook 37 a actel electronic mail 36 telephone 36 web-based technical support 35 website 35 addressing scheme 9 b big lut 6 architecture 12 c configuration evaluation version 32 configuration file, sample 31 configuration parameters 26 configuration text file 6 contacting actel customer service 35 electronic mail 36 telephone 36 web-based technical support 35 cordic architecture 13 coredds device utilization and performance 7 overview 5 simplified view 5 test configurations 8 typical application 6 customer service 35 d dithering 15 e evaluation version, installation 17 f frequency resolution 11 full version, installation 20 functional description 9 h hardware architectures 6 high-precision phase angle 9 i if modulator 6 implementation hints 17 installation evaluation version 17 full version 20 installation flow 17 interface descriptions 25 l licenses 17 lut-based dds 9 o output frequency 10 p parallel cordic 6 performance 7 phase accumulator 9 phase quantizer 15 place-and-route 23 port signals 25 index
38 coredds handbook index pre-synthesis simulation 22 product support 35 ? 36 customer service 35 electronic mail 36 technical support 35 telephone 36 website 35 q quarter period wave symmetry 9 s signal-to-noise ratio 11 small lut 6 architecture 13 spectral purity 11 spurious free dynamic range 11 synthesis 23 t technical support 35 test configurations 8 u utilization 7 v verification testbench 29 w web-based technical support 35

for more information about actel?s products, visit our website at http://www.actel.com actel corporation ? 2061 stierlin court ? m ountain view, ca 94043 usa customer service: 650.318.1010 ? customer applications center: 800.262.1060 actel europe ltd . ? dunlop house, riverside way ? camb erley, surrey gu15 3yl ? united kingdom phone +44 (0) 1276 401 450 ? fax +44 (0) 1276 401 490 actel japan ? exos ebisu bldg. 4f ? 1-24-14 ebisu shibuya-ku ? tokyo 150 ? japan phone +81.03.3445.7671 ? fax +81.03.3445.7668 ? www.jp.actel.com actel hong kong ? suite 2114, two pacific place ? 88 queensway, admiralty hong kong phone +852 2185 6460 ? fax +852 2185 6488 ? www.actel.com.cn 50200078-0 /9.06

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